About the role#
Intel is seeking a PhD intern to join the Foundry System Technology team. You will work on System Technology Co-optimization (STCO) to advance semiconductor and packaging manufacturing. The role focuses on evaluating 3D and 2.5D dis-aggregation schemes for memory and logic stacking.
What you'll do#
- Develop and improve STCO methodologies.
- Perform system-level evaluations of novel devices, interconnects, materials, and integration schemes.
- Collaborate with teams to drive innovation across various product architectures.
- Evaluate dis-aggregation schemes using solder microbumps or hybrid bonding.
What you'll need#
- Active Ph.D. candidacy in Electrical Engineering, Electronics Engineering, Computer Architecture and Design, or a related field.
- 1-2+ years of research experience in areas such as system architecture modeling, digital circuit analysis, or VLSI physical layout.
- Familiarity with IC design and physical layout tools, specifically Cadence Virtuoso or Synopsis Fusion Compiler.
Location & details#
- Locations: Hillsboro, OR; Santa Clara, CA; or Austin, TX.
- Term: Summer 2027 (minimum 3 months).
- Work Modality: Hybrid.
- Employment Type: Full-time paid internship.
About Intel Corporation
Intel Corporation designs and manufactures semiconductors. The company focuses on artificial intelligence, autonomous driving, and non-volatile memory solutions. It operates as a public company with over 110,000 employees. The headquarters are in Santa Clara, California, with major office locations across the United States, Israel, France, Singapore, and Poland.
How to get in at Intel Corporation
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