About the role#
As an RTL Intern, you will contribute to the design of microarchitecture and the implementation of logic in Verilog. You will work directly with cutting-edge machine learning architectures and participate in the full design cycle, ranging from microarchitecture discussions to synthesis and timing feedback.
What you'll do#
- Implement logic in Verilog and contribute to RTL block development.
- Engage in the complete design cycle, including synthesis and timing feedback.
- Collaborate with team members on microarchitecture discussions.
- Learn about transformers and modern artificial intelligence hardware.
What you'll need#
- Progress toward a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field.
- Familiarity with high-speed digital logic and ASIC or SoC design concepts.
- Experience with SystemVerilog, UVM, or Python.
- Proficiency in verification work and writing test benches.
- Familiarity with physical design flows, tooling, clocking, and reset schemes.
- Exposure to numerical representations and transformer models is considered a plus.
Location & details#
- Location: San Jose, California.
- Term: 12-week paid internship from June to August 2026.
- Work Modality: On-site.
- Benefits: Includes housing support for those relocating and daily lunch and dinner provided at the office.
About Etched
Etched operates in the computer hardware manufacturing industry. The company builds frontier inference clusters. Founded in 2022, it maintains its headquarters in San Jose, California. The organization is privately held and employs approximately 496 people.
How to get in at Etched
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