About the role#
As an RTL Intern at Etched, you will contribute to the development of custom hardware designed for transformer-based AI inference. You will work within our ASIC department, collaborating with engineers to design microarchitecture and implement logic. This position offers the opportunity to participate in the full design cycle, from initial microarchitecture discussions through to synthesis and timing feedback.
What you'll do#
- Design microarchitecture and implement logic using Verilog.
- Contribute to RTL block development.
- Work with cutting-edge machine learning architectures.
- Participate in the full design cycle, including synthesis and timing feedback.
- Learn about transformers and modern artificial intelligence hardware implementations.
What you'll need#
- Progress towards a Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
- Familiarity with high-speed digital logic.
- Exposure to ASIC or SoC design concepts.
- Familiarity with SystemVerilog, UVM, or Python.
- Experience with verification work and writing test benches.
- Familiarity with physical design flows and tooling.
- Ability to learn quickly in a high-autonomy environment.
- Preferred experience includes familiarity with transformer models, machine learning, numerical representations, and clocking or reset schemes.
Location & details#
- Location: San Jose, California.
- Term: Summer 2026 (12-week internship, June – August).
- Modality: Full-time, on-site.
- Compensation: This is a paid internship including housing support and daily lunch and dinner.
- Note: Visa sponsorship is not provided for this role.
