DV Intern

About the role#

As a Design Verification intern, you will ensure the custom IPs powering our chips—including systolic arrays, DMA engines, and NoCs—are robust, high-performance, and silicon-ready. This role requires technical ability and the drive to tackle complex verification challenges.

What you'll do#

• Ensure custom IPs are robust, high-performance, and silicon-ready.
• Collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.
• Tackle complex verification challenges.

What you'll need#

• Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field.
• Familiarity with high-speed digital logic.
• Familiarity with SystemVerilog, UVM, or Python.
• Familiarity with verification work and writing test benches.
• Familiarity with physical design flows and tooling.

Location & details#

• Location: San Jose, California.
• Term: Summer 2026 (12-week program).
• Work Modality: On-site.
• Employment Type: Full-time.
• Compensation: Paid internship.