About the role#
As a Ph.D. Intern in Advanced Packaging and Physical Integration, you will work on packaging design and analysis challenges for production AI accelerator and connectivity platforms. This role places you inside active development efforts, working on problems that are inseparable from your doctoral research. You will gain experience solving packaging problems that ship inside advanced AI silicon.
What you'll do#
- Perform signal integrity (SI) and power integrity (PI) analysis for high-speed interfaces, including 224G SerDes, die-to-die interconnects, and HBM interfaces.
- Develop and execute thermal and mechanical simulation models for advanced 2.5D and 3D chiplet packages.
- Evaluate heat dissipation, warpage, and reliability under production conditions.
- Contribute to physical design and layout of package substrates, RDL interposers, and chiplet integration schemes.
- Collaborate with chip design, assembly, and test engineering teams to validate packaging assumptions against silicon measurements and production data.
- Use industry-standard EDA and simulation tools, such as Ansys and Cadence Sigrity, to model and optimize package-level performance.
- Present analysis results and design recommendations to the engineering team.
What you'll need#
- Currently enrolled in a Ph.D. program in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.
- Research focus in advanced packaging, signal/power integrity, thermal engineering, or heterogeneous integration.
- Hands-on research experience in semiconductor packaging, signal integrity, or a closely related physical design discipline.
- Ability to apply fundamentals in electromagnetics, heat transfer, or materials mechanics to build and interpret simulation models.
- Proficiency with simulation tools such as Ansys HFSS, Ansys Icepak, or Cadence Sigrity.
- Experience with high-speed serial interface SI analysis at 100G/lane speeds or above.
- Familiarity with advanced packaging technologies including CoWoS, FOPLP, RDL interposers, or flip-chip BGA.
- Exposure to co-packaged optics (CPO) integration, optical engine assembly, or photonic-electronic co-design.
- Experience with power delivery network (PDN) design and analysis.
- Familiarity with design-for-manufacturing (DFM) and reliability considerations for chiplet-based multi-die packages.
Location & details#
- Locations: Santa Clara, Irvine, Westlake Village, CA; Austin, TX; Chandler, AZ; Westborough, MA; Burlington, VT.
- Modality: On-site.
- Employment: Full-time, paid internship.
- Term: Rolling.
About Marvell Technology
Marvell Technology is a semiconductor manufacturing company based in Santa Clara, California. It provides hardware solutions for cloud infrastructure, data centers, and enterprise systems. The company employs over 11,000 people across global offices. Its technical focus includes wireless and wireline connectivity, storage, and consumer electronics.
How to get in at Marvell Technology
Applying early for an internship at Marvell Technology provides a distinct advantage, as recruiters often review candidates before the applicant pool becomes unmanageable. Intern Insider sends an instant alert the moment a role matching your target is published anywhere, so you apply among the first and get seen before the pile grows. Reaching out to the right person can also help you stand out from the crowd. Intern Insider surfaces the recruiters behind the company roles so you can reach out directly to ask about the position or a referral, which materially improves response rates.
