About the role#
The Design Technology Co-Optimization (DTCO) team works at the intersection of process technology, standard cell architecture, and design implementation. As an intern, you will gain hands-on experience assessing and optimizing power, performance, and area (PPA) at the standard cell and logic block level. You will collaborate with engineers to evaluate design tradeoffs and develop methodologies that improve silicon outcomes using industry-standard tools and AI-enabled automation.
What you'll do#
- Implement standard cell logic blocks using physical design tools, including floorplanning, placement, clock tree synthesis, routing, and PPA optimization.
- Analyze and benchmark power, performance, and area across standard cell libraries and logic block configurations to find improvements.
- Perform static timing analysis, investigate setup and hold timing violations, and support timing closure.
- Run physical verification checks, including DRC, LVS, and IR-drop analysis, while helping resolve design issues.
- Use Generative AI, AI Assistants, and Agentic AI to automate data collection, reporting, and workflow optimization for PPA analysis.
What you'll need#
- Current pursuit of a B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related field with an expected graduation date of Fall 2025 or later.
- Understanding of VLSI design concepts, CMOS circuits, digital logic, and the ASIC physical design flow.
- Experience with scripting languages like Python, Perl, or TCL from coursework, research, or projects.
- Strong analytical, problem-solving, and debugging skills.
- Academic or project experience with place-and-route tools such as Synopsys ICC2 or Cadence Innovus.
- Exposure to static timing analysis platforms like PrimeTime or Tempus.
- Knowledge of design constraints (SDC), LEF/DEF formats, physical implementation methodologies, and power intent standards like UPF or CPF.
- Experience applying AI, Large Language Models, or AI-assisted coding tools to improve engineering productivity.
Location & details#
- Location: Boise, Idaho
- Employment Type: Part-time
- Modality: On-site
- Compensation: This is a paid internship
About Micron Technology
Micron Technology produces memory and storage solutions including DRAM, NAND, and NOR products. The company operates as a public organization with over 43,000 employees. Founded in 1978, it maintains its headquarters in Boise, Idaho. Micron serves various markets ranging from data centers to mobile devices.
How to get in at Micron Technology
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