DFT Intern

About the role#

We are looking for a Design for Test (DFT) Intern to join our Digital Design team. You will work alongside experienced engineers to support the development and implementation of DFT methodologies for SoC designs. This role provides hands-on experience with scan insertion, ATPG, MBIST, and other test-related flows in a semiconductor environment.

What you'll do#

• Assist in the implementation of DFT techniques including scan insertion, boundary scan, and memory BIST.
• Support ATPG pattern generation and validation using industry-standard tools.
• Help with test coverage analysis and the debug of test patterns.
• Collaborate with RTL designers and verification teams to ensure testability requirements are met.
• Contribute to the automation of DFT flows using Python, Perl, or TCL.
• Document DFT methodologies, test plans, and results.

What you'll need#

• Currently pursuing a Bachelor or Master degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong understanding of digital logic design and VLSI fundamentals.
• Familiarity with Verilog or VHDL and scripting languages like Python, Perl, or TCL.
• Exposure to DFT concepts such as scan chains, ATPG, and BIST.
• Experience with EDA tools from Synopsys, Cadence, or Mentor Graphics.
• Coursework or project experience in DFT or digital IC design.
• Knowledge of STA, synthesis, and RTL verification.
• Familiarity with Linux or Unix environments.
• Excellent problem-solving skills, attention to detail, and the ability to work well in a team.

Location & details#

• Location: Austin, Texas.
• Term: Summer 2027.
• Modality: On-site and hybrid options available.
• Employment: Full-time paid internship.
• Note: You must be returning to school or graduating at the conclusion of the internship term to be eligible.