About the role#
We are looking for a research intern to focus on loop engineering. You will work on closed-loop flows that automate, optimize, and explore SoC designs, specifically AI-assisted hardware/software co-design flows. You will work alongside a full-time researcher to own a scoped research question. Your work involves building or extending the loop, running experiments, and documenting what the results mean for design automation.
What you'll do#
- Study how a design loop should be structured, including which steps belong in it, what feedback each step returns, and how results from search, verification, and physical design drive the next iteration.
- Implement the loop using languages and tools like Chisel and XLS, alongside simulation, software build, and physical-design tools.
- Apply the loop to an SoC problem, such as microarchitectural exploration, RTL implementation and verification, or power, performance, and area optimization.
- Compare loop designs based on the quality of the design point, search cost, reproducibility, reuse, and failure diagnosis.
- Make the loop reliable enough to rerun by creating clear interfaces between steps, caching results, adding regression checks, and generating reports that support a conclusion.
What you'll need#
- Progress toward a bachelor’s, master’s, or Ph.D. in electrical engineering, computer engineering, computer science, or a related field.
- Coursework or project experience in loop engineering, computer architecture, digital design, VLSI, or electronic design automation.
- Fluency in Python and comfort reading or changing an existing codebase.
- Ability to pose a small research question, keep a record of changes, and explain the results.
- Exposure to RTL (Verilog, SystemVerilog, Chisel, or XLS) or an SoC design framework is preferred.
- Experience with an architecture simulator or RTL simulation.
- Familiarity with an AI-assisted hardware/software co-design loop framework, such as CHIA, or scripted hardware design, verification, or design-space exploration flows.
Location & details#
- Location: San Jose, California.
- Work modality: On-site.
- Duration: 6 months.
- Schedule: 40 hours per week.
- Compensation: $35/hr - $45/hr.
- This is a paid, full-time position.
About SK hynix memory solutions America Inc.
SK hynix memory solutions America Inc. designs and develops storage solutions including NAND flash memory and solid state drives. The company formed in 2012 following the acquisition of Link A Media Devices Corporation by SK hynix. It operates as a subsidiary focused on controller hardware, firmware, and memory systems architecture. Based in San Jose, the company employs over 300 people and serves clients in the enterprise, mobile, and client storage markets.
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