About the role#
Kepler Communications is seeking an FPGA Digital Design Engineering Intern to contribute to the development of our next generation of satellites and earth stations. You will write RTL code that supports our mission to provide real-time on-orbit connectivity. This is a full-time, paid internship opportunity.
What you'll do#
- Maintain and add functionality to the existing FPGA code base, including code for software-defined radio and software-defined network systems.
- Design custom IP for new features on Kepler satellites and ground stations.
- Add support for new communication interfaces and sensors, such as SPI, I2C, and UART.
- Work with high-speed FPGA interfaces including JESD204b, 10G Ethernet, and Aurora.
What you'll need#
- Completion of at least 2 years in an Electrical or Computer Engineering degree program or equivalent.
- Proficiency in Verilog, SystemVerilog, or VHDL, with the expectation to work in SystemVerilog.
- Current enrollment in an undergraduate program at a Canadian post-secondary institution, with plans to return to studies after the internship.
- Availability for a full-time internship lasting 4 to 16 months, beginning in January 2027.
- Ability to work from the Toronto office at least 2 to 3 days per week.
Location & details#
- Location: Toronto, Ontario, Canada.
- Term: Winter 2027.
- Work Modality: On-site.
