About the role#
Cadence is seeking an intern or co-op to join the Interface IP team in Toronto. This position focuses on the development of next generation PCIe SERDES Phy IP. You will work alongside digital, verification, physical design, analog, and system engineers to gain exposure to the full digital ASIC development cycle, from RTL design to tape-out. This is a full-time, paid position.
What you'll do#
- Perform RTL coding, simulation, and verification.
- Develop and improve design and verification flow automation.
- Compile timing constraints and execute logic synthesis.
- Collaborate with experienced engineers on project management, build flows, and environment maintenance.
- Interface with the application engineering team to address design integration issues and customer support requests.
What you'll need#
- Completion of your third year of study in Electrical Engineering, Computer Engineering, or Engineering Science.
- A strong academic background.
- Excellent verbal and written communication skills.
- Ability to work effectively within a team environment.
- A proactive approach to identifying problems and proposing technical solutions.
- Experience with Verilog HDL is preferred.
- Proficiency in scripting with Python, Perl, or similar object-oriented languages is preferred.
Location & details#
- Location: Toronto, Ontario, Canada.
- Work Modality: On-site.
- Employment Type: Full-time.
- Term: Rolling.
About Cadence
Cadence is a research services company founded in 2014. It provides language solutions for investors and consultants to help them gain business insights across language barriers. The firm offers services including due diligence, management calls, and market research for finance professionals. It maintains teams in Los Angeles, Latvia, Beijing, and Singapore with a staff of 11 to 50 employees.
How to get in at Cadence
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