About the role#
This is a full-time, on-site internship based in San Jose, California, for the Fall 2026 semester. You will join the DDR IP group to focus on post-silicon validation. The role involves testing internal silicon test chips to ensure they meet performance standards.
What you'll do#
- Validate the system-level and electrical performance of internal silicon test chips.
- Collaborate with analog and digital design teams to debug silicon issues.
- Write clear characterization reports based on your findings.
- Work across teams to maintain product reliability and support successful deployment.
What you'll need#
- Current enrollment in a Bachelor or Master degree program in electrical engineering.
- Zero to 2 years of relevant work experience.
- Strong fundamentals in analog and digital electronics, RTL, signal integrity, and control systems.
- Excellent written and verbal communication skills.
- Ability to work effectively in a team environment.
- Experience with script-based test automation in Python or C is a plus.
- Prior experience in the hardware semiconductor or electronics industry is a plus.
Location & details#
- Location: San Jose, California.
- Modality: On-site.
- Term: Fall 2026.
- Compensation: $40 to $69 per hour, with potential for additional incentive compensation such as bonus, equity, and benefits.
- Requirements: Candidates must have legal authorization to work in the United States. Local candidates are preferred.
About Cadence
Cadence is a research services company founded in 2014. It provides language solutions for investors and consultants to help them gain business insights across language barriers. The firm offers services including due diligence, management calls, and market research for finance professionals. It maintains teams in Los Angeles, Latvia, Beijing, and Singapore with a staff of 11 to 50 employees.
How to get in at Cadence
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