CPU IP Design & Verification Intern – RISC-V Processor Development

About the role#

Join the MIPS CPU IP Engineering organization for hands-on experience in the design and verification of advanced RISC-V processor IP. You will work with CPU architects, RTL designers, and verification engineers on CPU microarchitecture, RTL implementation, functional verification, performance analysis, automation, and debug. This is a full-time summer 2027 internship.

What you'll do#

• Support RISC-V CPU microarchitecture and SystemVerilog RTL design and development.
• Contribute to CPU functions including instruction fetch and decode, execution, load/store, caches, memory interfaces, control and status registers, exceptions, and interrupts.
• Develop verification tests, assertions, checkers, and functional coverage for CPU features.
• Run CPU simulations and regressions and debug failures using logs, architectural traces, and waveforms.
• Verify processor functionality across instructions, privilege modes, memory operations, and architectural corner cases.
• Support CPU power, performance, and area analysis and optimization.
• Develop Python, C/C++, or scripting-based automation to improve design, verification, regression, and debug productivity.
• Document technical results and communicate findings to the engineering team.
• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements.

What you'll need#

• At least a sophomore at time of application.
• Actively pursuing a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.
• At least an overall 3.0 GPA and good academic standing.
• English language fluency in written and verbal forms.
• Ability to work at least 40 hours per week.
• Coursework or project experience in digital logic design and computer architecture.
• Familiarity with Verilog or SystemVerilog.
• Understanding of CPU fundamentals including pipelines, instruction execution, loads/stores, caches, and memory hierarchy.
• Programming or scripting experience with Python, C/C++, or similar languages.
• Strong analytical, problem-solving, and debugging skills.
• Preferred: Prior internship experience, leadership experience, project management skills, and knowledge of RISC-V ISA.
• Preferred: Experience with SystemVerilog/UVM, simulation, waveform debug, Git, Linux, and assembly-language programming.
• Preferred: Exposure to synthesis, lint, clock-domain crossing analysis, formal verification, or timing analysis.

Location & details#

• Locations: Austin, Texas or Santa Clara, California.
• Work Modality: On-site.
• Term: Summer 2027.
• Status: Paid, full-time.