About the role#
The Digital Logic + Design Verification Graduate Co-Op Program provides hands-on experience in the development of next-generation semiconductor technologies. Participants work on high-performance chips designed for AI data centers and enterprise-level applications. This role offers exposure to the full design lifecycle, ranging from RTL development to simulation, verification, and silicon validation in a collaborative, cross-functional environment.
What you'll do#
- Contribute to RTL design and implementation of digital logic blocks for ASICs and SoCs.
- Support micro-architecture development, design specifications, and implementation.
- Assist with synthesis, timing analysis, and design reviews.
- Develop and execute verification test plans for digital and SoC designs.
- Build simulation environments, testbenches, and verification components.
- Debug simulation failures and analyze coverage to ensure functional correctness.
- Use industry-standard tools such as Verilog, SystemVerilog, and scripting languages to automate workflows.
What you'll need#
- Current enrollment in a Master’s or PhD program in Electrical Engineering, Computer Engineering, or a related field.
- A strong foundation in digital logic design and computer architecture.
- Familiarity with HDL languages, specifically Verilog or SystemVerilog.
- Strong analytical, problem-solving, and communication skills.
- Exposure to UVM or formal verification methodologies is preferred.
- Experience with RTL design, simulation, FPGA-based projects, or scripting languages (Python, Perl, TCL, or shell) is a plus.
Location & details#
- Location: Santa Clara, California.
- Term: Fall 2026.
- Modality: This is a full-time, on-site role requiring presence in the office five days a week.
- Compensation: This is a paid position with an expected base pay range of $35–$70 per hour, determined by skills, experience, and qualifications.
