Digital Logic + Design Verification Graduate Co-Op Program

About the role#

The Digital Logic + Design Verification Graduate Co-Op Program provides hands-on experience in developing semiconductor technologies for AI data centers and enterprise applications. Co-ops gain exposure to the full design lifecycle, including RTL development, simulation, verification, and silicon validation, while working alongside global engineering teams.

What you'll do#

• Contribute to RTL design and implementation of digital logic blocks for ASICs and SoCs.
• Support micro-architecture development, design specifications, and design reviews.
• Develop and execute verification test plans for digital and SoC designs.
• Build simulation environments, testbenches, and verification components.
• Debug simulation failures and analyze coverage to ensure functional correctness.
• Assist with synthesis and timing analysis.
• Automate workflows and analyze data using Python or similar scripting languages.

What you'll need#

• Current enrollment in a Master’s or PhD program in Electrical Engineering, Computer Engineering, or a related field.
• Strong foundation in digital logic design and computer architecture.
• Familiarity with HDL languages such as Verilog or SystemVerilog.
• Strong problem-solving, analytical, and communication skills.
• Exposure to UVM or formal verification methodologies is preferred.
• Experience with RTL design, simulation, FPGA-based projects, or SoC design concepts is a plus.

Location & details#

• Location: Santa Clara, California.
• Term: Fall 2026.
• Modality: On-site (five days a week).
• Compensation: Paid position with an expected base pay range of $35 - $70 per hour.
• Eligibility: This role requires eligibility to access technology and software subject to U.S. export control laws.