About the role#
This is a full-time, paid internship for Summer 2027 based in Santa Clara, California. You will join the Compute and Custom Solutions DFT team to work on Design for Test architecture and methodology. You will gain hands-on experience with complex SoC designs and industry tools while contributing to the development of silicon solutions for data center, enterprise, and automotive markets.
What you'll do#
- Develop an understanding of block-level and chip-top DFT and pattern-generation flows.
- Execute DFT insertion, pattern generation, and verification for Scan, MBIST, Boundary Scan, and IP macro test.
- Run DFT checks and analyze results to resolve testability issues and improve coverage.
- Support DFT flow automation using Python, Shell, or Tcl scripting.
- Contribute to documentation and methodology improvements.
- Present your project results to the team at the end of the internship.
What you'll need#
- Currently pursuing a Master's degree in Computer Engineering, Electrical Engineering, or a related field.
- Understanding of digital logic design using Verilog or System Verilog.
- Knowledge of DFT concepts, JTAG standards, and Boundary Scan implementation.
- Programming and scripting experience in Python, Shell, or Tcl.
- Effective teamwork and communication skills.
- Familiarity with Scan test, memory BIST/BISR, and functional test is preferred.
- Knowledge of AI-assisted tools for coding and automation is a plus.
Location & details#
- Location: Santa Clara, CA.
- Modality: On-site.
- Term: Summer 2027.
- Employment: Full-time internship.
- This role does not offer sponsorship.
About Marvell Technology
Marvell Technology is a semiconductor manufacturing company based in Santa Clara, California. It provides hardware solutions for cloud infrastructure, data centers, and enterprise systems. The company employs over 11,000 people across global offices. Its technical focus includes wireless and wireline connectivity, storage, and consumer electronics.
How to get in at Marvell Technology
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