R&D DSP/FPGA Design Automation Intern

About the role#

We are looking for an R&D intern to help develop and demonstrate a scalable, AI-assisted workflow for FPGA-based digital signal processing systems. This role sits at the intersection of signal processing, digital design, and software development. You will gain experience across the full FPGA development lifecycle while investigating how AI-assisted engineering can improve development speed, reuse, and consistency.

What you'll do#

• Build reusable, parameterized FPGA components for DSP, including MACs, FIFOs, adder trees, coefficient memories, delay elements, and numeric conversion blocks.
• Translate DSP and system requirements into FPGA architecture and implementation specifications.
• Design and verify RTL using Verilog, SystemVerilog, VHDL, or equivalent languages.
• Write bit-accurate or fixed-point reference models to validate FPGA implementations.
• Assemble components into a representative streaming DSP subsystem.
• Create automated simulation and verification tests covering numerical accuracy, reset behavior, streaming interfaces, backpressure, and parameter boundaries.
• Support synthesis, timing analysis, resource evaluation, and optimization.
• Use Python or similar languages to automate design, testing, data collection, and reporting.
• Investigate AI-assisted development tools across FPGA architecture, implementation, verification, and documentation, while defining objective ways to measure output quality.
• Analyze results to identify functional, numerical, timing, or resource limitations.
• Collaborate with DSP, FPGA, software, and system engineers in design reviews.
• Document interfaces, parameter constraints, and verification findings.
• Present results and recommendations to the engineering team at the end of the internship.

What you'll need#

• Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Coursework, project work, or job experience in DSP or digital system design.
• Understanding of digital logic, synchronous design, pipelining, and FSMs.
• Experience with at least one HDL or hardware-construction language such as Verilog, SystemVerilog, VHDL, or Chisel.
• Experience with Python, MATLAB, or C/C++ for modeling or automation.
• Familiarity with fixed-point arithmetic, quantization, or numerical implementation of DSP algorithms.
• Ability to turn requirements into an implementable design and communicate technical conclusions clearly.
• Strong problem-solving and teamwork skills.
• Interest in FPGA tradeoffs regarding throughput, latency, timing, and resource usage.
• Desirable experience includes working with Xilinx/AMD or Intel tools, streaming interfaces, FIR filters, cocotb, Git, CI, and AI-assisted engineering tools.

Location & details#

• Location: Santa Rosa, California.
• Modality: On-site.
• This is a paid, full-time internship.
• Visa sponsorship is not available for this position.