CPU IP Design & Verification Intern – RISC-V Processor Development

Company: MIPS Holding Inc Title: CPU IP Design & Verification Intern – RISC-V Processor Development (Summer 2027) Location: USA - California - Santa Clara, United States of America Posted Date: Posted Today Employment Type: Full time Sidebar Info: We shape what's essential At GlobalFoundries you will find a vibrant work environment where collaboration and innovation thrive. Our diverse and global team shares a culture of respect and inclusivity, representing the best in the industry. We celebrate success together and are united by our dedication to excellence and our desire to improve and empower the world.

Job Description: About GlobalFoundries GlobalFoundries (GF) is a leading manufacturer of essential semiconductors, enabling AI at scale from the cloud to the physical world. Through deep partnerships with customers, GF delivers differentiated, powerefficient and highperformance solutions for highgrowth markets. GF is a trusted and holistic technology partner for customers around the world. GF’s talented, global team remains focused every day on security, longevity and sustainability. For more information, visit  Internship Program Overview: Our Interns & Co-ops are our entry-level talent pipeline for GF across the globe. Our goal is to provide students with a meaningful work experience that will equip them with the skills to embark on a career in the fast-paced and growing semiconductor industry after graduation. As an intern at GF, you’ll experience one-on-one mentorship, work assignments that prioritize your growth and potential, professional development opportunities, and the chance to network with executives. Summary of Role: Join the MIPS CPU IP Engineering organization for hands-on experience in the design and verification of advanced RISC-V processor IP. You will work with CPU architects, RTL designers, and verification engineers on CPU microarchitecture, RTL implementation, functional verification, performance analysis, automation, and debug in Austin, Texas or Santa Clara, California. Essential Responsibilities include: Support RISC-V CPU microarchitecture and SystemVerilog RTL design and development. Contribute to CPU functions including instruction fetch and decode, execution, load/store, caches and memory interfaces, control and status registers, exceptions, and interrupts. Develop verification tests, assertions, checkers, and functional coverage for CPU features. Run CPU simulations and regressions and debug failures using logs, architectural traces, and waveforms. Verify processor functionality across instructions, privilege modes, memory operations, and architectural corner cases. Support CPU power, performance, and area analysis and optimization. Develop Python, C/C++, or scripting-based automation to improve design, verification, regression, and debug productivity. Document technical results and communicate findings to the engineering team. Other Responsibilities: Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs. Required Qualifications: Education – At least a sophomore at time of application and actively pursuing a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field through an accredited degree program during the time of internship. Must have at least an overall 3.0 GPA and be in good academic standing. Language Fluency - English (Written & Verbal) Ability to work at least 40 hours per week during the internship. Coursework or project experience in digital logic design and computer architecture. Familiarity with Verilog or SystemVerilog. Understanding of CPU fundamentals including pipelines, instruction execution, loads/stores, caches, and memory hierarchy. Programming or scripting experience with Python, C/C++, or similar languages. Strong analytical, problem-solving, and debugging skills. Preferred Qualifications: Prior related internship or co-op experience Demonstrated prior leadership experience in the workplace, school projects, competitions, etc. Strong interest in leveraging AI tools and emerging technologies to enhance productivity, streamline workflows, and support effective decision-making. Project management skills, i.e., the ability to innovate and execute on solutions that matter; the ability to navigate ambiguity. Strong written and verbal communication skills Strong planning & organizational skills Knowledge of the RISC-V Instruction Set Architecture (ISA). Experience with SystemVerilog/UVM, assertions, functional coverage, or constrained-random verification. CPU architecture, microarchitecture, FPGA, ASIC, or processor-design project experience. Familiarity with caches, memory subsystems, privilege modes, exceptions, interrupts, or virtual memory. Experience with simulation, waveform debug, Git, and Linux. Exposure to synthesis, lint, clock-domain crossing analysis, formal verification, or timing analysis. Assembly-language programming experience. Ability to work effectively in a collaborative engineering team. #InternshipProgramUS  Expected Salary Range $20.00 - $40.00 Expected Salary Range$0.00 - $0.00The exact Salary will be determined based on qualifications, experience and location.If you need a reasonable accommodation for any part of the employment process, please contact us by email at and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.  An offer with GlobalFoundries is conditioned upon the successful completion of pre-employment conditions, as applicable, and subject to applicable laws and regulations.  GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people. Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory.  All policies and processes which pertain to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law