About the role#
As a DFT Intern, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams, contribute to DFT verification, and develop flows for various ATPG fault models. This is a 12-week paid internship that offers direct mentorship from engineers and the chance to work on hardware for frontier intelligence.
What you'll do#
- Refine DFT flow automation to support chip-level regression on Caelius.
- Collaborate with frontend and backend design teams.
- Contribute to DFT verification, including MBIST, Scan, BSCAN, and SSN simulations.
- Develop flows for ATPG fault models.
What you'll need#
- Progress towards a Bachelor's, Master's, or PhD in electrical engineering, computer engineering, or a related field.
- Familiarity with Verilog or SystemVerilog.
- Knowledge of digital logic design fundamentals and ASIC or SoC design concepts.
- Understanding of standard ASIC design flow steps like synthesis, STA, and DFT.
- Scripting experience in Python, Tcl, or another language.
- Ability to learn about transformers and artificial intelligence.
- Knowledge of DFT concepts such as scan insertion, scan compression, and MBIST.
- Experience with Tessent or similar DFT tooling.
- Familiarity with ATPG fault models including SAF, TDF, BDF, IDDQ, and PDF.
- Exposure to DFT flow automation or regression infrastructure.
- Familiarity with clocking and reset schemes.
Location & details#
- Location: San Jose, California.
- Modality: On-site.
- Terms: Fall 2026, Winter 2027, or Summer 2027.
- The role includes daily lunch and dinner at the office and housing support for those relocating.
About Etched
Etched operates in the computer hardware manufacturing industry. The company builds frontier inference clusters. Founded in 2022, it maintains its headquarters in San Jose, California. The organization is privately held and employs approximately 496 people.
How to get in at Etched
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