About the role#
The Silicon Solutions Group (SSG) at Cadence is seeking a Design Engineering Intern to contribute to the development of the Janus NoC IP product. This role involves collaboration with Design, Verification, and Physical Design teams to support the creation of configurable and extensible IP solutions for modern system-on-chip (SoC) applications.
What you'll do#
- Perform Digital Design tasks including RTL implementation of micro-architecture using System Verilog.
- Simulate and debug RTL logic.
- Execute synthesis, place and route, and other Electronic Design Automation (EDA) tool workflows to meet timing, area, and power objectives.
- Assist with Design Verification by developing test plans and writing functional tests using UVM.
- Create verification monitors using SVA, debug failures, analyze coverage, and script verification flows.
What you'll need#
- Current enrollment in an MS or BS program in Electrical Engineering, Computer Engineering, or a related field.
- Strong understanding of Digital Design or Design Verification fundamentals.
- Proficiency in automation using Tcl, Perl, or shell scripting.
- Excellent oral and written communication skills.
- Exposure to design automation tools is considered an asset.
Location & details#
- Location: San Jose, California.
- Term: Fall 2026.
- Modality: On-site.
- Employment type: Full-time, paid internship.
