About the role#
Join the Physical Design team to help deliver next-generation SSD controller chips. You will collaborate with experienced engineers to transform RTL designs into functional physical layouts, gaining hands-on experience in the complete ASIC flow from synthesis to tape-out.
What you'll do#
- Execute ASIC physical design implementation flows, including floorplanning, placement, clock tree synthesis (CTS), and routing.
- Perform static timing analysis (STA) and resolve setup and hold timing violations.
- Run and analyze design rule checks (DRC), layout versus schematic (LVS) checks, and IR-Drop analysis to ensure design integrity.
- Assist in optimizing power, performance, and area (PPA) metrics using industry-standard EDA tools.
- Develop and maintain P&R, physical verification, and IR-EM flows.
- Collaborate with front-end design and verification teams to integrate RTL changes and resolve physical design constraints.
- Generate and maintain physical design scripts, utilities, and documentation.
What you'll need#
- Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Foundational understanding of VLSI design concepts, CMOS circuit design, and digital logic.
- Familiarity with the basic stages of the ASIC physical design flow.
- Academic or project experience with scripting languages such as Python, Perl, or TCL.
- Strong analytical, problem-solving, and attention-to-detail skills.
- Preferred: Experience with EDA tools (e.g., Synopsys ICC2, Cadence Innovus), STA tools (e.g., PrimeTime, Tempus), design constraints (SDC), and library exchange formats (LEF/DEF).
- Preferred: Knowledge of low-power design techniques (UPF/CPF) and familiarity with AI/LLM tools for automating EDA scripting and workflow optimization.
Location & details#
- Location: San Jose, California
- Modality: On-site
- Compensation: $35/hr - $45/hr
- Employment Type: Full-time
- Term: Rolling
