About the role#
This internship offers an opportunity to contribute to ongoing ASIC projects within a semiconductor manufacturing environment. The role requires a 6-month, full-time commitment working on-site in San Jose, California.
What you'll do#
- Manage design databases, including checking in golden files, reverting changes, and merging files.
- Develop RTL logic using Verilog syntax.
- Execute simulations using Synopsys VCS.
- Debug simulation environments to resolve compilation failures, simulation hangs, and functional issues.
- Collaborate with designers and verification engineers to identify and implement technical solutions.
What you'll need#
- Current enrollment in or completion of a BS/MS degree in Electrical Engineering, Electronics, Computer Science, or a related field.
- Proficiency in Verilog and SystemVerilog programming.
- Strong communication skills for a collaborative work environment.
- A reliable work ethic, including punctuality and commitment to meeting deadlines.
- Ability to work 40 hours per week, Monday through Friday.
- Understanding of the ASIC/FPGA workflow from concept to silicon is preferred.
- Scripting skills in languages such as Python, Perl, or Tcl are a plus.
Location & details#
- Location: San Jose, California.
- Modality: 100% on-site.
- Duration: 6 months.
- Schedule: 40 hours per week.
- Compensation: $35/hr - $45/hr.
