About the role#
The Design Technology Co-Optimization team works where process technology, standard cell architecture, and design implementation meet. You will focus on optimizing power, performance, and area for advanced memory products. This role involves collaborating with library, RTL, and physical design engineers to evaluate tradeoffs and improve silicon outcomes. You will gain hands-on experience in physical design, timing closure, and design analysis using industry-standard tools and AI-enabled automation.
What you'll do#
- Implement standard cell logic blocks using tools for floorplanning, placement, clock tree synthesis, routing, and PPA assessment.
- Analyze and benchmark power, performance, and area across standard cell libraries and logic block configurations to find improvement opportunities.
- Perform static timing analysis, investigate timing violations, and support timing closure.
- Run physical verification checks, including DRC, LVS, and IR-drop analysis, while helping resolve design issues.
- Use Generative AI, AI Assistants, and Agentic AI solutions to automate data collection, reporting, and workflow optimization for PPA analysis.
What you'll need#
- Currently pursuing a B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related field with an expected graduation date of Fall 2025 or later.
- Understanding of VLSI design, CMOS circuits, digital logic, and the ASIC physical design flow.
- Experience with scripting languages like Python, Perl, or TCL through coursework, research, or projects.
- Strong analytical, problem-solving, and debugging skills.
- Hands-on experience with place-and-route tools like Synopsys ICC2 or Cadence Innovus.
- Exposure to static timing analysis tools such as PrimeTime or Tempus.
- Knowledge of design constraints, LEF/DEF formats, and physical implementation methodologies.
- Understanding of low-power design techniques and power intent standards like UPF or CPF.
- Experience using AI, Large Language Models, or AI-assisted coding tools to improve engineering productivity.
Location & details#
- Location: Boise, Idaho, United States.
- Modality: On-site.
- Employment type: Full-time.
- Term: Rolling.
About Micron Technology
Micron Technology produces memory and storage solutions including DRAM, NAND, and NOR products. The company operates as a public organization with over 43,000 employees. Founded in 1978, it maintains its headquarters in Boise, Idaho. Micron serves various markets ranging from data centers to mobile devices.
How to get in at Micron Technology
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