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    Design Verification Intern

    Quadric · Burlingame, California, United States

    Summer 2026On-sitePaidPosted 2026-05-18
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    About the role#

    Quadric is seeking a Design Verification Intern to contribute to the development of our general-purpose neural processing unit (GPNPU) architecture. This role provides hands-on experience working alongside experts in AI and semiconductor technology, with opportunities for mentorship and project ownership.

    What you'll do#

    • Collaborate with architects and designers to document test plans, write and debug tests, and generate coverage.
    • Assist in the verification of designs using SystemVerilog or SystemC.
    • Utilize scripting languages such as Python and leverage LLMs to complete technical tasks.

    What you'll need#

    • Currently pursuing a Bachelor's, Master's, or PhD in Computer Science, Electrical Engineering, or a related field.
    • Proficiency in SystemVerilog, SystemC, or C/C++.
    • Familiarity with verification methodologies for CPU or GPU designs.
    • Demonstrated capability in problem-solving, debugging, and clear technical communication.
    • Coursework or project experience in Computer Architecture, RTL Design, ML systems, or performance engineering.
    • Exposure to assembly or low-level code generation is preferred.

    Location & details#

    • Location: Burlingame, California.
    • Term: Summer 2026.
    • Modality: On-site.
    • Compensation: $45.00 to $60.00 per hour, depending on experience and education.
    • Employment type: Full-time.
    Relevant fields:Computer ScienceElectrical Engineering

    About Quadric

    Founded in 2017 and headquartered in Burlingame, California, Quadric is a privately held semiconductor company with 51 to 200 employees. The firm develops and licenses the Chimera General Purpose Neural Processing Unit, an AI processor architecture designed for on-device inference. This technology allows developers to run both C++ code and machine learning tasks on a single scalable processor core. The hardware supports performance levels ranging from 1 to 864 TOPS by integrating scalar, vector, and matrix processing capabilities.

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