About the role#
Join the ASIC team as a Design Verification Intern. This role focuses on high-performance compute and networking standards within advanced CMOS process nodes. You will work alongside the ASIC team on projects involving digital logic and computer architecture.
What you'll do#
- Design and verify blocks using leading-edge methodology and tools.
- Collaborate directly with the ASIC team on silicon engineering projects.
- Utilize scripting languages such as Python and Perl to support verification workflows.
- Apply knowledge of digital logic and computer architecture to high-performance networking standards.
What you'll need#
- Completed at least 3rd year of study in Computer Engineering or Electrical/Electronic Engineering.
- Minimum GPA of 3.5.
- Hands-on experience with RTL design languages and tools, including Verilog and System Verilog.
- Experience with C/C++.
- Strong analytical and debugging skills with a detail-oriented approach.
- Preferred: Knowledge of high-speed interfaces (PCIe, DDR, HBM, Serdes), communication interfaces (SPI, I2C, JTAG), System Verilog test benches (UVM), and Synopsys EDA tools.
Location & details#
- Location: Toronto, Ontario, Canada.
- Term: Summer 2026.
- Modality: On-site.
- Employment: Full-time, paid.
- Authorization: Must be authorized to work in Canada.
