About the role#
Join the ASIC team as a Design Verification Intern for the Summer 2026 term. This role focuses on high-performance compute and networking standards within advanced CMOS process nodes. You will work on projects involving digital logic and computer architecture while collaborating closely with the ASIC engineering team.
What you'll do#
- Design and verify blocks using industry-leading methodologies and tools.
- Develop and maintain test benches and verification environments.
- Apply scripting languages such as Python or Perl to automate tasks and improve efficiency.
- Engage in technical projects related to digital logic and computer architecture.
What you'll need#
- Completion of at least the 3rd year of a degree in Computer Engineering or Electrical/Electronic Engineering.
- A minimum GPA of 3.5.
- Hands-on experience with RTL design languages and tools, specifically Verilog and System Verilog.
- Familiarity with C/C++ and scripting languages like Python or Perl.
- Strong analytical and debugging skills with a focus on detail.
- Authorization to work in Canada.
- Preferred experience includes knowledge of high-speed interfaces (PCIe, DDR, HBM, Serdes), communication interfaces (SPI, I2C, JTAG), System Verilog test benches (UVM), and Synopsys EDA tools.
Location & details#
- Location: Toronto, Ontario, Canada.
- Modality: On-site.
- Commitment: Full-time.
- Term: Summer 2026.
About Astera Labs
Astera Labs is a semiconductor company based in San Jose, California. Founded in 2017, the firm develops connectivity solutions for rack-scale AI infrastructure. It serves hyperscalers and ecosystem partners by integrating hardware technologies with its proprietary software suite. The company currently employs over 1,100 people across global office locations.
How to get in at Astera Labs
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